Apparatus and method for protecting electronic circuits

ABSTRACT

Apparatuses and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. application Ser. No. ______, entitled APPARATUS AND METHOD FOR ELECTRONIC SYSTEMS RELIABILITY (Inventors: Javier A. Salcedo, David Casey, and Graham McCorkell; Atty. Docket No. ADINC.037A, filed on even date herewith), the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field

Embodiments of the invention relate to electronic systems, and more particularly, to protection circuits for electronic systems.

2. Description of the Related Technology

Certain electronic systems can be exposed to a transient signal event, or an electrical signal of a relatively short duration having rapidly changing voltage and high power. Transient signal events can include, for example, electrostatic discharge (ESD) events arising from the abrupt release of charge from an object or person to an electronic system.

Transient signal events can damage integrated circuits (ICs) inside an electronic system due to overvoltage conditions and/or high levels of power dissipation over relatively small areas of the ICs. High power dissipation can increase IC temperature, and can lead to numerous problems, such as gate oxide punch-through, junction damage, metal damage, and surface charge accumulation. Moreover, transient signal events can induce latch-up (in other words, inadvertent creation of a low-impedance path), thereby disrupting the functioning of the IC and potentially causing permanent damage to the IC. Thus, there is a need to provide an IC with protection from such transient signal events.

SUMMARY

In one embodiment, an apparatus for providing transient signal protection comprises a substrate, a well formed on a first surface of the substrate, an emitter region formed in the well, a collector region formed at least partially in the well and spaced away from the emitter region to define a spacing, a first spacer and a second spacer positioned adjacent the well between the emitter and the collector, and a conductive plate positioned adjacent the well and between the first spacer and the second spacer. The well has a doping of a first type, and the well is configured to operate as a base for a first transistor. The emitter region has a doping of a second type opposite that of the first type, and the emitter region is configured to operate as an emitter for the first transistor. The collector region has a doping of the second type, and the collector region is configured to operate as a collector of the first transistor. The first spacer and the second spacer are dielectric, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.

In another embodiment, an apparatus for providing transient signal protection comprises a substrate means, a well means formed on a first surface of the substrate means, an emitter means formed in the well means, a collector means formed at least partially in the well means and spaced away from the emitter means to define a spacing, a first spacing means and a second spacing means positioned adjacent the well means between the emitter means and the collector means, and a plate means positioned adjacent the well means and between the first spacing means and the second spacing means. The well means has a doping of a first type, and the well means is configured to operate as a base for a first transistor. The emitter means has a doping of a second type opposite that of the first type, and the emitter means is configured to operate as an emitter for the first transistor. The collector means has a doping of the second type, and the collector means is configured to operate as a collector of the first transistor, and a doping adjacent the first spacing means, the second spacing means, and the plate means consists essentially of the first type.

In another embodiment, a method for providing protection from transient electrical events comprises providing a substrate, forming a well having a doping of a first type on a first surface of the substrate, forming a plate adjacent the well, and forming first and second spacers adjacent the well. The plate is positioned between the first and second spacers, and a length of the plate and a length of the first and second spacers define a first distance. The method further includes forming an emitter and a collector at least partially in the well, wherein the emitter and the collector have a doping of a second type opposite that of the first type, and wherein the emitter and collector are spaced apart by the first distance. Additionally, the method includes configuring the well, the emitter and the collector, respectively, to operate as the base, emitter, and collector of a bipolar transistor for providing protection from transient electrical events. The method does not include forming a lightly doped drain (LDD) region in the well.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of one example of an electronic system including integrated circuits (ICs).

FIG. 2 is a schematic block diagram of an integrated circuit including pad circuits according to some embodiments.

FIG. 3A is a graph of one example of pad circuit current versus transient signal voltage.

FIG. 3B is a graph of another example of pad circuit current versus transient signal voltage.

FIG. 4A is a schematic block diagram of a pad circuit in accordance with one embodiment.

FIG. 4B is a schematic block diagram of a pad circuit in accordance with another embodiment.

FIG. 5A is a circuit diagram illustrating a pad circuit building block in accordance with one embodiment.

FIG. 5B is a circuit diagram illustrating a pad circuit building block in accordance with another embodiment.

FIG. 5C is a circuit diagram illustrating a pad circuit building block in accordance with yet another embodiment.

FIG. 6A is a cross section of a conventional NMOS transistor having a lightly doped drain (LDD) structure.

FIG. 6B is a cross section of an NPN bipolar transistor in accordance with one embodiment.

FIG. 6C is a cross section of a PNP bipolar transistor in accordance with another embodiment.

FIG. 7A is a circuit diagram illustrating a pad circuit building block in accordance with yet another embodiment.

FIG. 7B is a cross section of one implementation of the pad circuit building block of FIG. 7A.

FIG. 8A is a circuit diagram illustrating a pad circuit building block in accordance with yet another embodiment.

FIG. 8B is a cross section of one implementation of the pad circuit building block of FIG. 8A.

FIG. 9A is a schematic block diagram of a pad circuit according to a first embodiment.

FIG. 9B is a circuit diagram of the pad circuit of FIG. 9A.

FIG. 10A is a schematic block diagram of a pad circuit according to a second embodiment.

FIG. 10B is a circuit diagram of the pad circuit of FIG. 10A.

FIG. 11A is a schematic block diagram of a pad circuit according to a third embodiment.

FIG. 11B is a circuit diagram of the pad circuit of FIG. 11A.

FIG. 12A is a schematic block diagram of a pad circuit according to a fourth embodiment.

FIG. 12B is a circuit diagram of the pad circuit of FIG. 12A.

FIG. 13A is a schematic block diagram of a pad circuit according to a fifth embodiment.

FIG. 13B is a circuit diagram of the pad circuit of FIG. 13A.

FIG. 14A is a schematic block diagram of a pad circuit according to a sixth embodiment.

FIG. 14B is a circuit diagram of the pad circuit of FIG. 14B.

FIG. 15 is a circuit diagram illustrating a pad circuit building block in accordance with yet another embodiment.

FIG. 16A is a schematic block diagram of a pad circuit according to a seventh embodiment.

FIG. 16B is a circuit diagram of the pad circuit of FIG. 16A.

FIG. 17A is a perspective view of one implementation of the pad circuit of FIG. 12B.

FIG. 17B is a cross section of the pad circuit of FIG. 17A taken along the line 17B-17B.

FIG. 17C is a cross section of the pad circuit of FIG. 17A taken along the line 17C-17C.

FIG. 17D is a cross section of the pad circuit of FIG. 17A taken along the line 17D-17D.

FIG. 17E is a top plan view of the active and polysilicon layers of the pad circuit of FIG. 17A.

FIG. 17F is a top plan view of the contact and first metal layers of the pad circuit of FIG. 17A.

FIG. 17G is a top plan view of the first metal layer and first via layer of the pad circuit of FIG. 17A.

FIG. 17H is a top plan view of the second metal layer and second via layer of the pad circuit of FIG. 17A.

FIG. 17I is a top plan view of the third metal layer of the pad circuit of FIG. 17A.

FIG. 18A is a perspective view of one implementation of the pad circuit of FIG. 11B.

FIG. 18B is a cross section of the pad circuit of FIG. 18A taken along the line 18B-18B.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description of certain embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways as defined and covered by the claims. In this description, reference is made to the drawings where like reference numerals indicate identical or functionally similar elements.

Electronic systems are typically configured to protect circuits or components therein from transient signal events. Furthermore, to help assure that an electronic system is reliable, manufacturers can test the electronic system under defined stress conditions, which can be described by standards set by various organizations, such as the Joint Electronic Device Engineering Council (JEDEC), the International Electrotechnical Commission (IEC), and the Automotive Engineering Council (AEC). The standards can cover a wide range of transient signal events, including ESD events.

Electronic circuit reliability can be improved by coupling pad protection circuits to the pads of an IC for transient signal protection. The pad circuits can be configured to maintain the voltage level at the pad within a predefined safe range. However, it can be difficult to provide pad circuits that meet reliability and performance requirements with low manufacturing cost and a relatively small circuit area.

An integrated circuit (IC) can have many pads, and different pads can be exposed to different voltage domains. Each voltage domain can have different performance and reliability requirements. For example, each voltage domain can have a different minimum operating voltage, maximum operating voltage, and constraint on leakage current. There is a need for providing IC protection pads operating over a multitude of voltage domains to enhance electronic circuit reliability for ICs in a simple and cost-effective manner.

Overview of Electronic Systems

FIG. 1 is a schematic block diagram of an electronic system 10, which can include one or more pad circuits according to an embodiment of the invention. The illustrated electronic system 10 includes a first IC 1, a second IC 2, and pins 4, 5, 6. As illustrated in FIG. 1, the pin 4 is electrically connected to the first IC 1 by a connection 7. The pin 5 is electrically connected to the second IC 2 by a connection 8. The electronic system 10 can also include pins electrically connected to both the first and second ICs 1, 2. For example, the illustrated pin 6 is electrically connected to the first and second ICs 1, 2 by a connection 9. Additionally, the first and second ICs 1, 2 can be electrically connected to one another by one or more connections internal to the electronic system 10, such as by connections 11 and 12. The first and second ICs 1, 2 can be exposed to user contact via, for example, the pins 4, 5, 6. The user contact can be through a relatively low-impedance connection.

The first and second ICs 1, 2 can be exposed to transient signal events, such as ESD events, which can cause IC damage and induce latch-up. For example, the connection 11 can receive a device-level transient signal event 14, and/or the pin 6 can receive a system-level transient signal event 16. The transient signal events 14, 16 can travel along the connections 11, 9, respectively, and can be received at the pads of the first and second ICs 1, 2.

In some embodiments, the first and second ICs 1, 2 can include pads, and can be provided with pad circuits configured to ensure reliability of the ICs by maintaining the voltage level at the pads within a selected range, which can vary from pad to pad. For example, either or both of the first and second ICs 1, 2 can include one or more pads configured to operate over a multitude of voltage domains or current bias conditions, each having varying performance and reliability requirements.

Overview of Power Management ICs

In some embodiments, one or more pad circuits can be employed in an IC, such as the first IC 1 of FIG. 1, and can be configured to provide transient signal protection to one or more internal circuits of the IC. The pad circuit can be configured to divert a current associated with a transient signal event received on a pad of the IC to other nodes or pads of the IC, thereby providing transient signal protection, as will be described in further detail below. The current can be shunted from, for example, a low-impedance output pad, a high-impedance input pad, or a low-impedance power or ground pad, to a low impedance pad or node of the IC. When no transient signal event is present, the pad circuit can remain in a high-impedance/low-leakage state, thereby reducing or minimizing static power dissipation resulting from leakage current and improving the operation of leakage sensitive circuitry, as will be described in detail below.

In other embodiments, one or more pad circuits can be provided in a single IC (for example, the first IC 1 of FIG. 1), and can be configured to provide transient signal protection for another component (for example, the second IC 2 of FIG. 1). The first IC 1 can be physically separated from the second IC 2, or it can be encapsulated in a common package with the second IC 2. In such embodiments, one or more pad circuits can be placed in a stand-alone IC, in a common package for system-on-a-package applications, or integrated with an IC in a common semiconductor substrate for system-on-a-chip applications.

FIG. 2 is a schematic block diagram of one example of an integrated circuit (IC) including pad circuits according to some embodiments. The IC 20 can be a power management IC, which can include, for example, pad circuits 22 a-22 p, a pad controller 23, comparators 27 a-27 h, a multiplexer 30, first and second OR gates 31 a, 31 b, an output logic 32, a clear logic 33, a voltage reference circuit 35, a timer 39, and pads 42 a-42 p. The power management IC 20 can be included in an electronic system, such as the electronic system 10 of FIG. 1, and can be, for example, the first IC 1 or the second IC 2. Depending on a design specification, not all of the illustrated components are necessary. For example, skilled artisans will appreciate that the pad controller 23 need not be included, that the power management IC 20 can be modified to monitor more or fewer voltage domains, and that the power management IC 20 can have more extensive or less extensive functionality.

Furthermore, although the pad circuits are illustrated in the context of the power management IC 20, the pad circuits can be employed in a wide array of ICs and other electronics having pads configured to operate over a multitude of voltage domains or current bias conditions.

The power management IC 20 can be configured to simultaneously monitor multiple voltage domains for overvoltage and undervoltage conditions, as will be described below. For example, the power management IC 20 can generate an overvoltage signal coupled to the pad 42 i (OVERVOLTAGE), which can indicate whether or not an overvoltage condition is detected on any of the pads 42 a-42 d (VH1, VH2, VH3, and VH4, respectively). Additionally, the power management IC 20 can generate an undervoltage signal coupled to the pad 42 j (UNDERVOLTAGE), which can indicate whether or not an undervoltage condition is detected on any of the pads 42 e-42 h (VL1, VL2, VL3, and VL4, respectively). Although the illustrated power management IC 20 is configured to monitor up to four voltage domains, skilled artisans will appreciate that this choice is merely illustrative, and that alternate embodiments of the power management IC 20 can be configured to be able to monitor more or fewer voltage domains, as well as to feature more extensive or less extensive functionality.

The power management IC 20 can aid in the integration and bias of ICs and other components of the electronic system 10. The power management IC 20 can also detect overvoltage conditions and/or undervoltage conditions which can endanger the proper operation of the electronic system 10. Additionally, the power management IC 20 can aid in reducing power consumption by detecting overvoltage conditions which can undesirably increase power consumption.

The power management IC 20 can be subject to stringent performance and design requirements. For example, the power management IC 20 can be subject to relatively tight constraints on leakage current in order to reduce static power dissipation and to improve performance for leakage-sensitive circuitry, as will be described below. Additionally, the power management IC 20 can be used to interact with multiple voltage domains, and thus should be able to handle relatively high input and output voltages without latching-up or sustaining physical damage. Moreover, there can be stringent requirements regarding the expense of the design and manufacture of the power management IC 20. Furthermore, in certain embodiments, configurability of the performance and design parameters of the power management IC 20 can be desirable, thereby permitting the power management IC 20 to be employed in a vast array of electronic systems and applications.

Each of the comparators 27 a-27 h can monitor an overvoltage or undervoltage condition of a voltage domain. This can be accomplished by providing a voltage from a voltage domain to a comparator. For example, a resistor divider (not shown in FIG. 2) having a series of resistors can be placed between a voltage supply of a voltage domain and a voltage reference, such as ground. A voltage can be tapped between the series of resistors and can be provided to a pad of the power management IC 20, such as, for example, the pad 42 a (VH1). The voltage received at the pad 42 a can be provided to the comparator 27 a, which in turn can compare the voltage received from the pad 42 a to a threshold voltage Vx. In one embodiment, the threshold voltage Vx is selected to be about 500 mV. By selecting the voltage provided to the pad 42 a (for example, by selecting the number and magnitude of the resistors in the divider), the output of the comparator 27 a can be configured to change when the voltage supply of a voltage domain exceeds a selected value. Likewise, by selecting the voltage provided to the pad 42 e in a similar manner, the output of the comparator 27 e can be configured to change when the supply of a voltage domain falls below a selected value.

As described above, the voltage provided to the pads 42 a-42 h can be provided from a resistor divider. The impedance of the resistors in the resistor divider can be relatively large (for example, tens of Mega-Ohms) so as to minimize system-level static power consumption. Thus, the accuracy of the resistor divider can be sensitive to the leakage of the pads 42 a-42 h, and there can be stringent performance requirements on the leakage current of the pads 42 a-42 h.

The first OR gate 31 a can determine if one or more of the comparators coupled to its inputs indicate that an overvoltage condition has been detected. Likewise, the second OR gate 31 b can determine if one or more of the comparators coupled to its inputs indicate that an undervoltage condition has been detected. In the illustrated embodiment, the outputs of comparators 27 a, 27 b are provided to the first OR gate 31 a, while the outputs of the comparators 27 e, 27 f are provided to the second OR gate 31 b.

Additionally, the first and second OR gates 31 a, 31 b can each receive signals from the multiplexer 30. The multiplexer 30 can allow overvoltage and undervoltage detection to be performed on voltage domains having a negative polarity with respect to the voltage received on the ground pad 42 o (GND), such that overvoltage and undervoltage relate to magnitudes or absolute values of voltage. In particular, the multiplexer 30 can select which comparator signals are provided to the first and second OR gates 31 a, 31 b in response to a select control signal received from the pad 42 p (SEL). For example, the multiplexer 30 can be configured to selectively provide the first OR gate 31 a with the output of the comparator 27 c or the comparator 27 g, and the output of the comparator 27 d or the comparator 27 h, based on a state of the select control signal received from the pad 42 p (SEL). Likewise, the multiplexer 30 can be configured to selectively provide the second OR gate 31 b with the output of the comparator 27 c or the comparator 27 g, and the output of the comparator 27 d or the comparator 27 h, based on a state of the select control signal received from the pad 42 p (SEL). By selecting which comparator outputs are provided to the first and second OR gates 31 a, 31 b, overvoltage and undervoltage detection can be performed on the voltages on the pads 42 c, 42 d and 42 g, 42 h, even for voltage domains having a negative polarity with respect to ground. The multiplexer 30 can be implemented with logic gates, with 3-state gates, or the like.

The output logic 32 can control the state of the pad 42 i (OVERVOLTAGE) and the pad 42 j (UNDERVOLTAGE). For example, the output logic 32 can indicate that an overvoltage or undervoltage condition has been detected based at least in part on the outputs of the first and second OR gates 31 a, 31 b. The output logic 32 can signal the detection of an overvoltage or undervoltage condition for a duration exceeding the time that the first or second OR gates 31 a, 31 b indicates that an overvoltage or undervoltage condition has been detected. For example, the output logic 32 can receive a signal from the timer 39, which can indicate the duration that the overvoltage or undervoltage condition should be asserted. The timer 39 can be electrically connected to the pad 42 m (TIMER) and can be configured to have a drive strength and corresponding drive resistance. The pad 42 m can be electrically connected to an external capacitor, which can have a variable capacitance to establish an RC time constant for determining the reset delay of the timer 39.

The output logic 32 can also be configured to communicate with the clear logic 33. The clear logic 33 can receive a clear control signal from pad 42 k (CLEAR). In response to the clear control signal, the output logic 32 can reset the state of the pads 42 i (OVERVOLTAGE) and 42 j (UNDERVOLTAGE) to indicate that no overvoltage or undervoltage condition has been detected.

The power management IC 20 can also provide an output reference voltage on pad 42l (V_(REF)). This voltage can be selected to be, for example, about 1 V. The output voltage reference can be used by other components of the electronic system in which the power management IC 20 is implemented (for example, the electronic system 10 of FIG. 1). For example, the reference voltage can be provided as a reference voltage to one end of a resistor divider configured to provide a voltage to the pads 42 a-42 h for overvoltage or undervoltage detection.

As described above, the power management IC 20 can be configured to monitor multiple voltage domains, for example, four voltage domains for overvoltage and undervoltage conditions. Each of the voltage domains can have the same or different operating conditions and parameters. Additionally, the power management IC 20 can include a multitude of output pads, such as the pad 42 i for indicating the detection of an overvoltage condition, the pad 42 j for indicating the detection of an undervoltage condition, the pad 42 p for providing the output voltage reference. The power management IC 20 can also include control pads, such as the pad 42 p (SEL), the pad 42 k (CLEAR), and the pad 42 m (TIMER). Furthermore, the power management IC 20 can include the power pad 42 n (Vcc) and the ground pad 42 o (GND).

In some embodiments, the electronic system (for example, the electronic system 10 of FIG. 1) having the pads 42 a-42 p can have different requirements for minimum operating voltage, maximum operating voltage, and leakage current for each of the pads 42 a-42 p. Thus, each of the pads 42 a-42 p described above can have different performance and design requirements. In order to meet reliability requirements across a wide variety of applications, it can be desirable that one or more of the pads 42 a-42 p have a pad circuit configured to protect the power management IC 20 from overvoltage conditions and latch-up. Furthermore, it can be desirable that each pad circuit 22 a-22 p is configurable to operate with different reliability and performance parameters, for example, by changing only metal layers during back-end processing, or by using the pad controller 23 after fabrication. This can advantageously permit the pad circuits 22 a-22 p to be configurable for a particular application without requiring a redesign of the power management IC 20.

FIG. 3A illustrates a graph 60 of one example of pad circuit current versus transient signal voltage. As described above, it can be desirable for each pad circuit 42 a-42 p to be configured to maintain the voltage level at the pad within a predefined safe range. Thus, the pad circuit can shunt a large portion of the current associated with the transient signal event before the voltage of the transient signal V_(TRANSIENT) reaches a voltage V_(FAILURE) that can cause damage to the power management IC 20. Additionally, the pad circuit can conduct a relatively low current at the normal operating voltage V_(OPERATING), thereby minimizing static power dissipation resulting from the leakage current I_(LEAKAGE) and improving the performance of leakage sensitive circuitry, such a resistor divider.

Furthermore, as shown in the graph 60, the pad circuit can transition from a high-impedance state Z_(H) to a low-impedance state Z_(L) when the voltage of the transient Signal V_(TRANSIENT) reaches the voltage V_(TRIGGER). Thereafter, the pad circuit can shunt a large current over a wide range of transient signal voltage levels. The pad circuit can remain in the low-impedance state Z_(L) as long as the transient signal voltage level is above a holding voltage V_(HOLDING) and the rate of voltage change is in the range of normal frequency operating conditions, rather than in the range of high frequency conditions and relatively fast rise and fall times which can be associated with a transient signal event. In certain embodiments, it can be desirable for the holding voltage V_(HOLDING) to be above the operating voltage V_(OPERATION) so that the pad circuit does not remain in the low-impedance state Z_(L) after passage of the transient signal event and a return to normal operating voltage levels.

FIG. 3B is a graph 62 of another example of pad circuit current versus transient signal voltage. As shown in FIG. 3B, a pad circuit can transition from a high-impedance state Z_(H) to a low-impedance state Z_(L) when the voltage of the transient signal V_(TRANSIENT) reaches the voltage V_(TRIGGER). Thereafter, the pad circuit can shunt a large current over a wide range of transient signal voltage levels. The pad circuit can remain in the low-impedance state Z_(L) as long as the transient signal voltage level is above a holding voltage V_(HOLDING). It can be desirable for the holding voltage V_(HOLDING) to be below the operating voltage V_(OPERATION) in order to provide enhanced protection against transient signal events and to reduce the circuit area needed to provide a desired pad shunting current. This technique can be employed, for example, in embodiments in which the holding current I_(HOLDING) exceeds the maximum current the pad can supply when biased at normal operating voltage levels. Thus, in certain embodiments, the pad circuit need not remain in the low-impedance state Z_(L) after passage of the transient signal event and a return to normal operating voltage levels, even when V_(OPERATION) exceeds V_(HOLDING), because the pad may not be able to supply a sufficient holding current I_(HOLDING) to retain the pad circuit in the low-impedance state Z_(L).

As described above, the operating and reliability parameters of a pad circuit can vary widely, depending on a particular application. For purposes of illustration only, one particular electronic system can have the characteristics shown in Table 1 below for selected pads of FIG. 2.

TABLE 1 V_(OPERATION) V_(HOLDING) V_(TRIGGER) I_(LEAKAGE) Pad Min Max Min Max Min Max Min Max VH1 0 V  8 V 9 V 13 V 16 V 20 V 0 nA 15 nA VH2 0 V  8 V 6 V 10 V 16 V 20 V 0 nA 15 nA VH3 0 V  8 V 3 V  7 V 16 V 20 V 0 nA 15 nA VH4 0 V 16 V 6 V 10 V 24 V 30 V 0 nA 15 nA Vcc 18 V  20 V 22 V  24 V 24 V 30 V 0 nA 10 nA OVERVOLTAGE 0 V 16 V 14 V  18 V 24 V 30 V 0 nA 15 nA UNDERVOLTAGE 0 V 16 V 8 V 12 V 24 V 30 V 0 nA 15 nA

There is a need for pad circuits which can be configured to meet the performance and design parameters of an electronic circuit or IC (such as the power management IC 20 of FIG. 2) required for a particular application. Furthermore, in certain embodiments, there is a need for pad circuits which can operate with different reliability and performance parameters, for example, by changing only metal layers, or by configuring the power management IC 20 post-fabrication by selecting the setting of a pad controller 23. This can advantageously permit pad circuits 42 a-42 p to be configured for a particular application without requiring a redesign of the power management IC 20. The pad controller 23 can employ metal or poly fuses to control the operation of an ESD tolerant switch, as will be described in further detail below.

IC Pad Circuits for Protection from Transient Signal Event

FIG. 4A is a schematic block diagram of a pad circuit 22 according to an embodiment of the invention. The illustrated pad circuit 22 includes a first building block 72, a second building block 74, and a third building block 76. The first, second, and third building blocks 72, 74, 76 can be connected end-to-end in a cascade configuration between a pad 42 and a node 82, and can be subcircuits of the pad circuit 22. Additional or fewer building blocks can be included in the cascade to achieve the desired reliability and performance parameters, as will be described in further detail below. The pad circuit 22 can be, for example, any of the pad circuits 22 a-22 p shown in FIG. 2, and the pad 42 can be any of the pads 42 a-42 p, including, for example, low-impedance output pads, high-impedance input pads, and low-impedance power pads. The node 82 can be, for example, a low impedance node or pad of the power management IC 20 configured to handle a relatively large shunted current.

The building blocks 72, 74, 76 can form a pad circuit that has characteristics shown in FIG. 3A or 3B. In one embodiment, the first, second and third building blocks 72, 74, 76 can be selected from a variety of types, such as a variety of electrically isolated clamp structures, so as to achieve the desired performance and reliability parameters for the pad circuit 22. For example, a first type of building block (Type A) can have a holding voltage V_(H) _(—) _(A) and a trigger voltage V_(T) _(—) _(A). A second type of building block (Type B) can have, for example, a trigger voltage V_(T) _(—) _(B) and a holding voltage V_(H) _(—) _(B). By arranging additional or fewer of each type of building block, the overall holding voltage and trigger voltage of embodiments of the pad circuit 22 can be selectively varied. As will be described below, the building block types can be selected such that, when combining i number of Type A building blocks and j number of Type B building blocks in a cascade configuration, the pad circuit 22 can have a trigger voltage V_(TRIGGER) roughly equal to about i*V_(T) _(—) _(A)+j*V_(T) _(—) _(B), and a holding voltage V_(HOLDING) roughly equal to about i*V_(H) _(—) _(A)+j*V_(H) _(—) _(B). Thus, by selecting the type and/or number of building blocks employed after manufacturing, and/or selecting the value of V_(H) _(—) _(A), V_(H) _(—) _(B), V_(T) _(—) _(A) and V_(T) _(—) _(B) during design of the building blocks, a scalable family of pad circuit embodiments can be created which can be adapted for a multitude of electronic systems and applications.

The design cost associated with designing the pad circuits can be reduced as compared to, for example, an approach in which different diode, bipolar, silicon controlled rectifier, and/or MOS devices are employed to achieve the reliability and performance requirements needed for each pad circuit. Moreover, in one embodiment, a first building block is placed below the pad and additional building blocks are placed in the vicinity of the pad. During back-end fabrication (for example, fabrication of metal layers), building blocks can be included in a cascade configuration with the first building block. Thus, each pad circuit 22 can be configured for a particular electronic system or application by changing the metal layers to control the building block configuration, as will be described below.

FIG. 4B is a schematic block diagram of a pad circuit in accordance with one embodiment. The illustrated pad circuit 22 includes a first building block 72, a second building block 74, and a third building block 76. The first, second, and third building blocks 72, 74, 76 can be connected end-to-end in a cascade configuration between a pad 42 and a node 82. Additional or fewer building blocks and blocks of a variety of types can be included in the cascade, as described earlier in connection with FIG. 4A.

Additionally, as illustrated in FIG. 4B, the pad controller 23 can be configured to control the connections between the cascaded building blocks. For example, the pad controller 23 can be configured to bypass the second building block 74, thus selectively omitting the second building block 74 from the cascade. In one embodiment, a first building block is formed below the pad and additional building blocks are formed in the vicinity of the pad. After completing both front-end and back-end fabrication, particular building blocks can be included in a cascade with the first building block using the pad controller 23. For example, the pad controller 23 can be configured to include or exclude particular building blocks, thereby configuring the pad circuit 22 to have the trigger voltage V_(TRIGGER) and holding voltage V_(HOLDING) desired for a particular application. In one embodiment, each pad circuit 22 can be individually controlled by the pad controller 23 to achieve the desired cascade. In alternative embodiments, groupings of pads can be collectively configured by the pad controller 23. This can be desirable, for example, when a particular group of pads, such as VH1 and VL1 of FIG. 2, may have similar performance and reliability requirements.

In one embodiment, the pad controller 23 is configured to use metal or poly fuses to control the operation of an ESD tolerant switch. The switch can be configured to bypass the operation of particular building blocks in the pad circuit 22. In an alternate embodiment, the pad controller 23 can include a multitude of fuse-controlled filaments that can be independently biased to configure each pad circuit 22 per combinations of building block types, such as the building block types which will be described later with reference to FIGS. 5A-5C.

Although FIGS. 4A and 4B were described in the context of Type A and Type B building blocks, additional building block types can be used. For example, a Type C building block can have a holding voltage V_(H) _(—) _(C) and a trigger voltage V_(T) _(—) _(C) that are different from the holding voltages and the trigger voltages, respectively, of the first and second types of building blocks. The pad circuit 22 can combine i number of Type A building blocks, j number of Type B building blocks, and k number of Type C building blocks such that the pad circuit 22 has a trigger voltage V_(TRIGGER) roughly equal to about i*V_(T) _(—) _(A)+j*V_(T) _(—) _(B)+k*V_(T) _(—) _(C), and a holding voltage V_(HOLDING) roughly equal to about i*V_(H) _(—) _(A)+j*V_(H) _(—) _(B)+k*V_(H) _(—) _(C). The inclusion of additional building block types can increase the multitude of configurations of the cascade at the expense of an increase in design complexity. Furthermore, the number of building blocks in the cascade can also be increased to provide additional configurations, provided that each building block remains properly biased at the increased trigger and holding voltages. For example, in an electrically isolated clamp embodiment in which a deep n-well layer provides electrical isolation between building blocks, the number of building blocks can be limited by the voltage level provided to the deep n-well to maintain electrical isolation.

FIGS. 5A-5C illustrate the circuits of a family of building block types, one or more of which can be employed as a building block type in the pad circuits of FIGS. 4A and 4B.

FIG. 5A is a circuit diagram illustrating a pad circuit building block (for example, the Type A building block described above in connection with FIGS. 4A and 4B) in accordance with one embodiment. The Type A building block 91 includes a resistor 101 and a NPN bipolar transistor 100 having an emitter, a base, and a collector. The resistor 101 includes a first end electrically connected to the base of the transistor 100, and a second end electrically connected to the emitter of the transistor 100. The resistor 101 can have, for example, a resistance between about 5Ω and about 55Ω. The collector of the transistor 100 can be electrically connected to another building block or to a pad 42. The emitter of the transistor 100 can be electrically connected to another building block or to a node 82.

FIG. 5B is a circuit diagram illustrating a pad circuit building block (for example, the Type B building block described above in connection with FIGS. 4A and 4B) in accordance with another embodiment. The Type B building block 92 includes a PNP bipolar transistor 102, an NPN bipolar transistor 103, a first resistor 104 and a second resistor 105. The PNP transistor 102 and the NPN transistor 103 each include an emitter, a base, and a collector. The first resistor 104 includes a first end electrically connected to the emitter of the PNP transistor 102, and a second end electrically connected to the base of the PNP transistor 102 and to the collector of the NPN transistor 103. The first resistor 104 can have, for example, a resistance between about 5Ω and about 35Ω. The second resistor 105 includes a first end electrically connected to the collector of the PNP transistor 102 and to the base of the NPN transistor 103, and a second end electrically connected to the emitter of the NPN transistor 103. The second resistor 105 can have, for example, a resistance between about 50Ω and about 250Ω. The emitter of the PNP transistor 102 can be electrically connected to another building block or to a pad 42. The emitter of the NPN transistor 103 can be connected to another building block or to a node 82.

As skilled artisans will appreciate, the PNP transistor 102 and NPN transistor 103 are configured to be in feedback. At a certain level of the collector current of the PNP transistor 102, the feedback between the PNP transistor 102 and the NPN transistor 103 can be regenerative and can cause the Type B building block 92 to enter a low-impedance state.

FIG. 5C is a circuit diagram illustrating a pad circuit building block (for example, the Type C building block described above in connection with FIGS. 4A-4B) in accordance with yet another embodiment. The Type C building block 93 includes a resistor 107 and a PNP bipolar transistor 106 having an emitter, a base, and a collector. A first end of the resistor 107 is electrically connected to the emitter of the transistor 106, and a second end is electrically connected to the base of the transistor 106. The resistor 107 can have, for example, a resistance between about 11Ω and about 85Ω. The emitter of the transistor 106 can be electrically connected to another building block or to a pad 42. The collector of the transistor 106 can be connected to another building block or to a node 82.

With reference to FIGS. 5A-5C, the trigger and holding voltages of the Type A, Type B, and Type C building blocks can be selected so as to aid in configuring the pad circuit 22 to have a trigger voltage V_(TRIGGER) and a holding voltage V_(HOLDING) desired for a particular electronic system or application. For example, the trigger voltage of the Type A building block V_(T) _(—) _(A) and the trigger voltage of the Type B building block V_(T) _(—) _(B) can be based on the collector-emitter breakdown voltage of the NPN transistor 100 and the NPN transistor 103, respectively. Additionally, the positive feedback between the NPN transistor 103 and the PNP transistor 102 in Type B Building block 92 can make the holding voltage V_(H) _(—) _(B) of the Type B building block 92 less than the holding voltage V_(H) _(—) _(A) of the Type A building block 91. Furthermore, the Type C building block can have a holding voltage V_(H) _(—) _(C) greater than either the holding voltage V_(H) _(—) _(A) or V_(H) _(—) _(B), and can have a trigger voltage V_(T) _(—) _(C) based on the collector-emitter breakdown voltage of the PNP transistor 106.

In one embodiment, the Type A building block 91 and the Type B building block 92 are configured to have about the same trigger voltage, V_(T) _(—) _(A)=V_(T) _(—) _(B) V_(T). Additionally, the positive feedback between the NPN transistor 103 and the PNP transistor 102 is employed to selectively decrease the holding voltage V_(H) _(—) _(B) of the Type B building block 92 relative to the holding voltage V_(H) _(—) _(A) of the Type A building block. Thus, in some embodiments, i number of Type A building blocks and j number of Type B building blocks can be combined in a cascade configuration to produce a pad circuit 22 having a trigger voltage V_(TRIGGER) roughly equal to about (i+j)*V_(T), and a holding voltage V_(HOLDING) roughly equal to about i*V_(H) _(—) _(A)+j*V_(H) _(—) _(B), where V_(H) _(—) _(B) is selected to be less than V_(H) _(—) _(A). This permits configurations having the same number of building blocks in the cascade to have about the same trigger voltage V_(TRIGGER). Additionally, the type of building blocks in the cascade can be selected to achieve the desired holding voltage V_(HOLDING) of the pad circuit 22.

Skilled artisans will appreciate that the desired trigger voltage and holding voltage of each building block type can be achieved by proper selection of a variety of parameters, including, for example, the geometries of the transistors, the common-emitter gain or “β” of the transistors, and by selecting the resistance of the resistors.

Bipolar Transistor Structures for Pad Circuits

FIGS. 6A-6C illustrate cross sections of various transistor structures. As will be described below, FIGS. 6B and 6C illustrate cross sections of transistor structures according to embodiments of the invention. These transistors can be used in pad circuit building blocks, even in processes lacking dedicated bipolar transistor masks.

FIG. 6A illustrates a cross section of a conventional NMOS transistor having a lightly doped drain (LDD) structure. The LDD NMOS transistor 120 is formed on a substrate 121 and includes an n+ drain region 122, an n+ source region 123, a gate 125, gate oxide 127, a lightly doped (n−) drain extension region 128, a lightly doped source extension region 129, and sidewall spacers 130.

The n+ drain region 122 can be more heavily doped than the n− drain extension region 128. The difference in doping can reduce the electric fields near the drain region, thereby improving the speed and reliability of the transistor 120 while lowering gate-drain capacitance and minimizing the injection of hot electrons into the gate 125. Likewise, the n+ source region 123 can be more heavily doped than the n−source extension region 129 and provide similar improvements to the transistor 120.

In a conventional LDD process, the gate electrode 125 is used as a mask for n− LDD implantation used to form the drain and source extension regions 128, 129. Thereafter, sidewall spacers 130 can be provided and employed as a mask for n+ implantation used to form the drain region 122 and the source region 123.

FIG. 6B illustrates a cross section of a parasitic NPN bipolar transistor in accordance with one embodiment. The illustrated parasitic NPN bipolar transistor 140 includes an emitter 141, a base 142 formed of a p-well, a collector 143, a plate 145, an oxide layer 147, an isolation layer 151, and sidewall spacers 150. The emitter 141, the collector 143, the plate 145, and the oxide layer 147 have structures similar to those of the drain region 122, the source region 123, the gate 125, and the oxide layer 127, respectively, of the conventional NMOS transistor 120 of FIG. 6A. In contrast to the LDD NMOS transistor 120 shown in FIG. 6A, the illustrated bipolar transistor 140 does not have structures similar to those of the source and drain extension regions of the NMOS transistor 120.

Removal of the source and drain extension regions can result in transistor conduction being dominated by a bipolar component, rather than by a FET component. In particular, when a voltage is applied to the plate 145, the inversion layer may not extend from the emitter 141 to the collector 143, and thus the FET component of the current can be weak. Thus, during an overvoltage condition, the parasitic NPN bipolar transistor 140 can serve as the primary conduction path, and the parasitic NPN bipolar transistor 140 can function similarly to a traditional bipolar transistor.

The resulting structure can have lower leakage than a conventional NMOS structure and withstand relatively large voltages without breakdown. Further, the resulting structure can be sized so as to employ the parasitic bipolar structure for transient signal protection without drawbacks, such as reduced reliability, typically encountered in high performance analog applications when degrading the standard MOS device characteristics. Since the parasitic NPN bipolar transistor 140 can be formed using a process used to create a conventional LDD MOS transistor, such as the NMOS transistor 120 of FIG. 6A, both the parasitic NPN bipolar transistor 140 and the LDD NMOS transistor 120 can be fabricated simultaneously on a common substrate.

The parasitic bipolar transistor 140 can have desirable properties for ESD protection and can be used in building blocks described above in connection with FIGS. 5A-5B. The use of the parasitic NPN bipolar transistor 140 can be desirable, for example, in a process which includes conventional LDD MOS transistors, but which lacks a dedicated bipolar process. In one embodiment, a single additional mask can be added during fabrication of transistors to determine which transistor structures receive the LDD implant and which do not.

The sidewall spacers 150 can be formed using, for example, an oxide, such as SiO₂, or a nitride. However, other sidewall spacer materials can be utilized in certain manufacturing processes. A distance x₁ between the emitter 141 and the plate 145 can be selected to be, for example, in a range of about 0.1 μm to 2.0 μm. A distance x₂ between the collector 143 and the plate 145 can be selected to be, for example, in a range of about 0.1 μm to 2.0 μm.

The plate 145 can be formed from a variety of materials, including, for example, doped or undoped polysilicon. Although the plate 145 is illustrated as a single layer, the plate 145 can include multiple layers, such as, for example, layers of polysilicon and silicide. In one embodiment, the plate 145 can have a plate length x₃ selected to be in a range of about 0.25 μm to about 0.6 μm, for example, about 0.5 μm. However, skilled artisans will appreciate that the length of the plate 145 can vary depending on the particular process and application. The plate 145 can be fowled over the oxide layer 147, which can correspond to, for example, any oxide layer dielectric known in the art or any oxide layer dielectric later discovered, including high-k oxide layers.

The emitter 141 and the collector 143 of the bipolar transistor 140 can be formed using a variety of materials, including for example, any n-type doping material. The spacing between the emitter 141 and the collector 143 can correspond to the sum of the distance x1, the distance x2, and the plate length x3. In one embodiment, the spacing between the emitter 141 and collector 143 is selected to be in the range of about 0.45 μm to about 4.6 μm. The doping between the emitter and the collector, both beneath the sidewall spacers 151 and the plate can consist essentially of n-type, which can result in transistor conduction being dominated by a bipolar component, rather than by a FET component. Thus, when a voltage is applied to the plate 145, the inversion layer may not extend from the emitter 141 to the collector 143, and thus the FET component of the current can be weak. Accordingly, during an overvoltage condition, the parasitic NPN bipolar transistor 140 can serve as the primary conduction path, and the parasitic NPN bipolar transistor 140 can function similarly to a traditional bipolar transistor.

The base 142 can be electrically isolated from the substrate 144 using a wide variety of techniques. In the illustrated embodiment, the isolation layer 151 is a deep n-well layer provided to electrically isolate the base 142 from the substrate 144. Persons of ordinary skill in the art will appreciate that a variety of techniques to provide electrical isolation are well known in the art and can be used in accordance with the teachings herein. For example, the isolation layer 151 can be an n-type buried layer or an isolation layer of a silicon-on-insulator (SOI) technology. The parasitic bipolar transistor 140 can undergo back end processing to form, for example, contacts and metallization. Skilled artisans will appreciate that various processes can be used for such back end processing.

FIG. 6C is a cross section of a PNP bipolar transistor 160 in accordance with one embodiment. The illustrated PNP bipolar transistor 160 includes an emitter 161, a base 162 formed of an n-well, a collector 163, a plate 165, an oxide layer 167, and sidewall spacers 170. The PNP bipolar transistor 160 can be formed in a manner similar to that of the NPN bipolar transistor 140 by selecting impurities with opposite polarity to that described above.

The parasitic NPN bipolar transistor 140 and the parasitic PNP bipolar transistor 160 can be formed by omitting the implantation of the LDD layer in a conventional MOS process. As will be described in detail below, the NPN bipolar transistor 140 and the PNP bipolar transistor 160 can be used in the building blocks of FIGS. 5A-5C, thereby permitting the fabrication of a family of pad circuit building blocks even with a process lacking dedicated bipolar masks. The building blocks can be cascaded to achieve the desired holding and trigger voltages for a pad circuit, such as the pad circuit 22 of FIGS. 4A and 4B.

Alternative Embodiments of IC Pad Circuits

FIGS. 7A-8B represent building block types, one or more of which can be employed as a building block type in the pad circuits of FIGS. 4A and 4B.

FIG. 7A is a circuit diagram illustrating a pad circuit building block in accordance with yet another embodiment. The illustrated Type A′ building block 201 can be connected in a cascade between a pad 42 and a node 82, and includes a first resistor 203, a second resistor 205, a diode 204, and a NPN bipolar transistor 202 having an emitter, a base, a collector, and a plate. The NPN bipolar transistor 202 can have the structure of the NPN bipolar transistor 140 of FIG. 6B.

The diode 204 includes an anode electrically connected to the node 82, and a cathode electrically connected to the collector of the NPN bipolar transistor 202 at a node N₁. The node N₁ can be electrically connected to another building block in a cascade, such as the cascade of FIG. 4A, or to the pad 42. The first resistor 203 includes a first end electrically connected to the base of the NPN bipolar transistor 202, and a second end electrically connected to the emitter of the NPN bipolar transistor 202 and to a first end of the second resistor 205 at a node N₂. The first resistor 203 can have, for example, a resistance between about 5Ω and about 55Ω. In one embodiment, described below with reference to FIG. 7B, the first resistor 203 is implemented using a multi-finger array to achieve the target resistance, such as an array of six fingers each having a resistance selected from the range of about 30Ω and about 320Ω. The node N₂ can be electrically connected to another building block in a cascade or to the node 82. The second resistor 205 includes a second end electrically connected to the plate of the NPN bipolar transistor 202. The second resistor 205 can have, for example, a resistance between about 50Ω and about 50 kΩ.

As was described before with reference to FIGS. 4A and 4B, the pad circuit 22 can be employed in, for example, any of the pad circuits 22 a-22 p shown in FIG. 2, and the pad 42 can be any of the pads 42 a-42 p, including, for example, low-impedance output pads, high-impedance input pads, and low-impedance power pads. The node 82 can be, for example, a low impedance node or pad of the power management IC 20 configured to handle a relatively large shunted current. A transient signal event can be received at the pad 42. If the transient signal event has a voltage which is negative with respect to the node 82, the diode 204 can provide current which can aid in protecting the power management IC 20.

If the transient signal event has a voltage that is positive with respect to the node 82, the NPN bipolar transistor 202 can aid in providing transient signal protection. The trigger voltage of the Type A′ building block V_(T) _(—) _(A)′ can be based on the collector-emitter breakdown voltage of the NPN bipolar transistor 202. Additionally, the plate and the collector of the NPN bipolar transistor 202 can function to fowl a capacitor, which can enhance how the NPN bipolar transistor 202 performs when a transient signal event having a positive voltage is received by increasing the displacement current, as will be described below.

If the transient signal event received on pad 42 causes the node N₁ to have a rate of change dV_(N1)/dt and the capacitance between the plate and the collector of the NPN bipolar transistor 202 has a value of C₂₀₂, a displacement current can be injected by the capacitor equal to about C₂₀₂*dV_(N1)/dt. A portion of this current can be injected in the base of the NPN bipolar transistor 202, which can increase the speed at which the Type A′ building block 201 provides transient signal protection. As described above, a transient signal event can be associated with fast rise and fall times (for example, from about 0.1 ns to about 1.0 ms) relative to the range of normal signal operating conditions. Thus, the NPN bipolar transistor 202 can be configured to have a trigger voltage which decreases in response to rates of voltage change associated with the very high frequency conditions of a transient signal event. During normal operation, the absence of the lightly doped drain (LDD) can make the leakage of the NPN bipolar transistor 202 relatively low, even over a relatively wide range of temperatures, for example, between about −40° C. and about 140° C.

FIG. 7B illustrates an annotated cross section of one implementation of the pad circuit building block of FIG. 7A. The illustrated Type A′ building block 201 includes a substrate 221, emitters 211 a-211 f, base 212, collectors 213 a-213 e, plates 215 a-215 j, base contacts 217 a, 217 b, n-wells 218 a, 218 b, deep n-well 219, and substrate contacts 220 a, 220 b. The cross section has been annotated to illustrate examples of circuit devices formed, such as parasitic NPN bipolar transistors 202 a-202 j, resistors 203 a, 203 b, and diodes 204 a, 204 b. The diagram is also annotated to show the second resistor 205, which can be formed using, for example, n-diffusion or poly (not shown in this Figure). The Type A′ building block 201 can undergo back end processing to form contacts and metallization. These details have been omitted from FIG. 7B for clarity.

The diodes 204 a, 204 b can be formed from the substrate 221 and n-wells 218 a, 218 b. For example, the diode 204 a has an anode formed from the substrate 221 and a cathode formed from the n-well 218 a. Similarly, the diode 204 b has an anode formed from the substrate 221 and a cathode formed from the n-well 218 b.

The NPN bipolar transistors 202 a-202 j can be formed from emitters 211 a-211 f, collectors 213 a-213 e, plates 215 a-215 j, and base 212. For example, the NPN bipolar transistor 202 a can be formed from the emitter 211 a, the plate 215 a, the collector 213 a, and the base 212. The NPN bipolar transistors 202 b-202 j can be formed in a similar manner from emitters 211 b-211 f, collectors 213 a-213 e, plates 215 b-215 j, and base 212. Additional details of the NPN bipolar transistors 202 a-202 j can be as described above with reference to FIG. 6B.

The base 212 can be electrically isolated from the substrate 221 using n-wells 218 a, 218 b and deep n-well 219. The n-wells 218 a, 218 b and deep n-well 219 can also provide electrically isolation of the building block from other building blocks. The n-well contacts 222 a, 222 b can form a guard ring around the Type A′ building block 201. The n-well contacts 222 a, 222 b can be contacted to a metal layer above by using multiple rows of contacts, thereby permitting the guard ring to be connected to the collectors 213 a-213 e through metal. The guard ring can eliminate the formation of unintended parasitic paths between the pad circuit and surrounding semiconductor components when integrated on-chip. Additionally, the substrate contacts 220 a, 220 b can form a substrate ring which can aid in protecting the Type A′ building block 201 from latch-up.

The resistors 203 a, 203 b can be formed from the resistance between the bases of NPN bipolar transistors 202 a-202 j and the base contacts 217 a, 217 b. The resistance along the paths between the bases of the NPN bipolar transistors 202 a-202 j and the base contacts 217 a, 217 b can be modeled by the resistors 203 a, 203 b.

Persons of ordinary skill in the art will appreciate that the cross-section shown in FIG. 7B can result in the formation of the circuit shown in FIG. 7A. For example, each of the emitters of the NPN bipolar transistors 202 a-202 j can be electrically connected together to form a common emitter. Likewise, each of the collectors, plates, and bases of the NPN bipolar transistors 202 a-202 j can be electrically connected together to form a common collector, a common plate, and a common base, respectively. Thus, each of the NPN bipolar transistors 202 a-202 j can be legs of the NPN bipolar transistor 202. Additionally, the diodes 204 a, 204 b can be represented by the diode 204, and the resistors 203 a, 203 b can be represented by the first resistor 203. The second resistor 205 can be formed using, for example, n-diffusion or poly (not shown in this Figure). Thus, FIG. 7B illustrates a cross section of an implementation of the pad circuit building block of FIG. 7A. Skilled artisans will appreciate that numerous layout implementations of the Type A′ building block 201 are possible.

As described earlier with reference to FIG. 7A, the capacitance between the plate and the collector of the NPN bipolar transistor 202 can result in a current which can be injected in the base of the NPN bipolar transistor 202. This can increase the speed at which the Type A′ building block 201 provides transient signal protection. The second resistor 205 can have a resistance selected to provide injection into the base of the NPN bipolar transistors at a frequency associated with a transient signal event. In one embodiment, the second resistor 205 can have a resistance in the range of about 200Ω to 50 kΩs.

Each of the NPN bipolar transistors 202 a-202 j can be legs of the NPN bipolar transistor 202 as described above. In one embodiment, each of the NPN bipolar transistors has a plate width (for example, the width of the plate 145 in a direction orthogonal to the plate length x₃ of FIG. 6B) between about 30 μm and 100 μm, so that the total plate width (the sum of the plates widths of all legs) is in the range of about 300 μm to 1,000 μm. In one embodiment, the plate length of each NPN bipolar transistors (for example, x₃ in FIG. 6B) is selected to be between about 0.25 μm and about 0.6 μm, for example, about 0.5 μm. Although the cross section shown in FIG. 7B illustrates the NPN bipolar transistor 202 as having ten legs, skilled artisans will appreciate that more or fewer legs can be selected depending on, for example, the desired dimensions of the pad circuit and the desired total plate width. In one embodiment described with reference to FIGS. 17A-17H, the number and width of the legs are selected so that the implementation of the Type A′ building block 201 can fit under a bonding pad.

FIG. 8A is a circuit diagram illustrating a pad circuit building block in accordance with yet another embodiment. The illustrated Type B′ building block 231 can be connected in a cascade between the pad 42 and the node 82, and includes a PNP transistor 232, a NPN bipolar transistor 233, a first resistor 234, a second resistor 235, a third resistor 236, and a diode 237. The PNP transistor 232 includes an emitter, a base, and a collector. The NPN bipolar transistor 233 includes an emitter, a base, a collector and a plate, and can have a structure similar to that of the NPN bipolar transistor 140 of FIG. 6B.

The diode 237 includes an anode electrically connected to the node 82, and a cathode electrically connected to a first end of the first resistor 234 and to the emitter of the PNP transistor 232 at a node N₃. The node N₃ can be electrically connected to another building block in a cascade, such as the cascade of FIG. 4A, or to the pad 42. The first resistor 234 also includes a second end electrically connected to the base of the PNP transistor 232 and to the collector of the NPN bipolar transistor 233. The first resistor 234 can have, for example, a resistance between about 5Ω and about 35Ω. In one embodiment, described below with reference to FIG. 8B, the first resistor 234 is implemented using a multi-finger array to achieve the target resistance, such as an array of two fingers each having a resistance selected from the range of about 10Ω and about 70Ω. The second resistor 235 includes a first end electrically connected to the collector of the PNP transistor 232 and to the base of the NPN bipolar transistor 233, and a second end electrically connected to the emitter of the NPN bipolar transistor 233 and to a first end of the third resistor 236 at a node N₄. The second resistor 235 can have, for example, a resistance between about 50Ω and about 250Ω. In one embodiment, described below with reference to FIG. 8B, the second resistor 235 is implemented using a multi-finger array to achieve the target resistance, such as an array of two fingers each having a resistance selected from the range of about 100Ω and about 500Ω. The node N₄ can be electrically connected to another building block in a cascade or to the node 82. The third resistor 236 includes a second end electrically connected to the plate of the NPN bipolar transistor 233. The third resistor 236 can have, for example, a resistance between about 200Ω and about 50 kΩ.

As was described before with reference to FIGS. 4A and 4B, the pad circuit 22 can be, for example, any of the pad circuits 22 a-22 p shown in FIG. 2, and the pad 42 can be any of the pads 42 a-42 p. The node 82 can be, for example, a low impedance node or pad of the power management IC 20 configured to handle a relatively large shunted current. A transient signal event can be received at the pad 42. If the transient signal event has a voltage that is negative with respect to the node 82, the diode 237 can provide current which can aid in protecting the power management IC 20.

If the transient signal event has a voltage which is positive with respect to the node 82, the PNP transistor 232 and the NPN bipolar transistor 233 can aid in providing transient signal protection. The trigger voltage of the Type B′ building block V_(T) _(—) _(B′) can be based on the collector-emitter breakdown voltage of the NPN bipolar transistor 233. Additionally, the positive feedback between the NPN bipolar transistor 233 and the PNP transistor 232 can make the holding voltage V_(T) _(—) _(B′) of the Type B′ building block 231 less than the holding voltage V_(H) _(—) _(A′) of the Type A′ building block 201 of FIG. 7A.

The plate and the collector of the NPN bipolar transistor 233 can function to form a capacitor which can enhance the performance of the NPN bipolar transistor 233 when a transient signal event having a positive voltage is received, as was described earlier. For example, a portion of this current can be injected in the base of the NPN bipolar transistor 233 through capacitive coupling, which can aid the speed at which the Type B′ building block 231 provides transient signal protection. Thus, the NPN bipolar transistor 233 can be configured to have a trigger voltage which is lower at rates of voltage change associated with the very high frequency conditions of a transient signal event. During normal operation, the absence of the lightly doped drain (LDD) can make the leakage of the NPN bipolar transistor 233 low, even at relatively high temperatures.

FIG. 8B is an annotated cross section of one implementation of the pad circuit building block of FIG. 8A. The illustrated Type B′ building block 231 includes NPN emitters 241 a, 241 b, NPN bases 242 a, 242 b, NPN collector contacts 243 a, 243 b, plates 245 a, 245 b, NPN base contacts 247 a, 247 b, PNP base 258, PNP base contacts 257 a, 257 b, n-wells 248 a, 248 b, deep n-well 249, and substrate contacts 250 a, 250 b. As illustrated, the NPN collector contacts 243 a, 243 b are each formed partially in a p-well and partially in an n-well. For example, the NPN collector contact 243 a is partially formed in the NPN base 242 a, and partially formed in the PNP base 258, and the NPN collector contact 243 b is partially formed in the NPN base 242 b and partially formed in the PNP base 258. The cross section has been annotated to show certain circuit components formed from the layout, including NPN bipolar transistors 233 a, 233 b, PNP transistors 232 a, 232 b, p-well resistors 235 a, 235 b, n-well resistors 234 a, 234 b, and diodes 237 a, 237 b. The diagram is also annotated to show the third resistor 236, which can be formed using, for example, n-diffusion (not shown in this Figure). The Type B′ building block 231 can undergo back end processing to form contacts and metallization. These details have been omitted from FIG. 8B for clarity.

The diodes 237 a, 237 b can be formed from substrate 251 and n-wells 248 a, 248 b. For example, the diode 237 a has an anode formed from the substrate 251 and a cathode formed from the n-well 248 a. The diode 237 b has an anode formed from the substrate 251 and a cathode formed from the n-well 248 b.

The NPN bipolar transistors 233 a, 233 b can be formed from NPN emitters 241 a, 241 b, PNP base 258, NPN collector contacts 243 a, 243 b, plates 245 a, 245 b, and NPN bases 242 a, 242 b. For example, the NPN bipolar transistor 233 a can be formed from the NPN emitter 241 a, the plate 245 a, the PNP base 258, the NPN collector contact 243 a, and the NPN base 242 a. Likewise, the NPN bipolar transistor 233 b can be formed from the NPN emitter 241 b, the plate 245 b, the PNP base 258, the NPN collector contact 243 b, and the NPN base 242 b. Although the NPN bipolar transistors 233 a, 233 b are connected to NPN collector contacts 243 a, 243 b, in the illustrated embodiment, the contacts 243 a, 243 b are not connected to metal layers, and thus the PNP base 258 can also serve as collectors for NPN bipolar transistors 233 a, 233 b. Additional details of the NPN bipolar transistors 233 a, 233 b can be found above with reference to FIG. 6B.

The NPN bases 242 a, 242 b can be electrically isolated using n-wells 248 a, 248 b, n-well of the PNP base 258, and deep n-well 249. The n-well contacts 252 a, 252 b can form part of a guard ring around the Type B′ building block 231. The substrate contacts 250 a, 250 b can form a portion of a substrate ring which can aid in protecting the Type B′ building block 231 from latch-up.

The p-well resistors 235 a, 235 b can be formed from the resistance between the bases of NPN bipolar transistors 233 a, 233 b and the base contacts 247 a, 247 b. Skilled artisans will appreciate that the p-wells of the bases 242 a, 242 b can have a resistivity along the electrical path between the bases of NPN bipolar transistors 233 a, 233 b and the base contacts 247 a, 247 b, which can be modeled by p-well resistors 235 a, 235 b.

The PNP transistors 232 a, 232 b can be formed from PNP emitters 254 a, 254 b, PNP base 258, and the NPN bases 242 a, 242 b. For example, the PNP transistor 232 a can have an emitter formed from the PNP emitter 254 a, a base formed from the PNP base 258, and a collector formed from the NPN base 242 a. Likewise, the PNP transistor 232 b can have an emitter formed from the PNP emitter 254 b, a base formed from the PNP base 258, and a collector formed from the NPN base 242 b.

The n-well resistors 234 a, 234 b can be formed from the resistance between the bases of PNP transistors 232 a, 232 b and the PNP base contacts 257 a, 257 b. Skilled artisans will appreciate that the n-well of the PNP base 258 can have a resistivity along the electrical path between the bases of PNP transistors 232 a, 232 b and the PNP base contacts 257 a, 257 b, which can be modeled by n-well resistors 234 a, 234 b.

Persons of ordinary skill in the art will appreciate that the cross-section shown in FIG. 8B can result in the formation of the circuit shown in FIG. 8A. For example, each of the NPN bipolar transistors 233 a, 233 b can be legs of the NPN bipolar transistor 233. Likewise, each of the PNP transistors 232 a, 232 b can be legs of the PNP transistor 232. Additionally, the diodes 237 a, 237 b can form the diode 237, the n-well resistors 234 a, 234 b can form the first resistor 234, and the p-well resistors 235 a, 235 b can form the second resistor 235. The third resistor 236 can be formed using, for example, re-diffusion or poly (not shown in this Figure). Thus, FIG. 8B is a cross section of one implementation of the of the pad circuit building block of FIG. 8A. Skilled artisans will appreciate that numerous variations of the Type B′ building block 201 are possible.

As was described above with reference to FIG. 8A, when a transient signal is present, the capacitance between the plate and the collector of the NPN bipolar transistor 233 can result in a current being injected in the base of the NPN bipolar transistor 233. This can aid the speed at which the Type B′ building block 231 provides transient signal protection. The third resistor 236 can have a resistance selected to provide injection into the base of the NPN bipolar transistor 233 at a frequency associated with a particular transient signal event. In one embodiment, the third resistor 236 has a resistance selected in the range of about 200Ω to 50 kΩs.

Each of the NPN bipolar transistors 233 a, 233 b can be legs of the NPN bipolar transistor 233. In one embodiment, each NPN bipolar transistor 233 a, 233 b has a plate width typically selected between about 30 μm and 50 μm, so that the total plate width of the NPN bipolar transistor 233 is in the range of about 60 μm to 100 μm. The length of each NPN bipolar transistor 233 a, 233 b can have a length selected between, for example, about 0.25 μm and 0.6 μm, for example, about 0.5 μm. Although the cross section in FIG. 8B shows the NPN bipolar transistor 233 as having two legs, skilled artisans will appreciate that additional or fewer legs can be selected depending on a variety of factors, including the desired pad circuit dimensions and the desired total plate width. In one embodiment described with reference to FIGS. 18A-18B, the number and width of the legs is selected so that two instantiations of the Type B′ building block 231 can fit under a bonding pad.

The PNP transistors 232 a, 232 b can be legs of the PNP transistor 232. Although the cross section illustrated in FIG. 8B shows the PNP transistor 232 as having two legs, skilled artisans will appreciate that additional or fewer legs can be selected depending on a variety of factors such as the manufacturing process and application.

With reference to FIGS. 4A, 4B, 7A, and 8A, the trigger voltages V_(T) _(—) _(A′), V_(T) _(—) _(B′) and the holding voltages V_(H) _(—) _(A′), V_(H) _(—) _(B′) of the Type A′ and Type B′ building blocks can be selected so that the pad circuit 22 has a trigger voltage V_(TRIGGER) and a holding voltage V_(HOLDING) desired for a particular electronic system or application. For example, i number of Type A′ building blocks and j number of Type B′ building blocks can be cascaded so that the pad circuit 22 has a trigger voltage V_(TRIGGER) roughly equal to about i*V_(T) _(—) _(A′)+j*V_(T) _(—) _(B′), and a holding voltage V_(HOLDING) roughly equal to about i*V_(H) _(—) _(A′)+j*V_(H) _(—) _(B′). By selecting the Type and number of building blocks employed, and/or by selecting the value of V_(H) _(—) _(A′), V_(H) _(—) _(B′), V_(T) _(—) _(A′) and V_(T) _(—) _(B′) during design of the building blocks, a scalable family of pad circuits can be created which can be adapted for a multitude of electronic systems and applications. The design cost associated with designing the pad circuits can be reduced as compared to, for example, an approach in which different diode, bipolar, silicon controlled rectifier and MOS devices are employed to achieve the reliability and performance requirements needed for each pad circuit. The desired trigger voltage and holding voltage of each building block type can be achieved by proper selection of a variety of parameters, including, for example, the geometries of the transistors, the common-emitter gain or “β” of the transistors, and by selecting the resistance of the resistors.

In one embodiment, the Type A′ building block 201 and the Type B′ building block 231 are configured to have about the same trigger voltage, V_(T) _(—) _(A′)=V_(T) _(—) _(B′)=V_(T′). Additionally, the positive feedback between the NPN bipolar transistor 233 and the PNP transistor 232 is employed to selectively decrease the holding voltage V_(H) _(—) _(B′) of the Type B′ building block 231 relative to the holding voltage V_(H) _(—) _(A′) of the Type A′ building block 201. Thus, i number of Type A′ building blocks and j number of Type B′ building blocks can be combined in a cascade configuration to produce a pad circuit 22 having a trigger voltage V_(TRIGGER) roughly equal to about (i+j)*V_(T′), and a holding voltage V_(HOLDING) roughly equal to about i*V_(H) _(—) _(A′)+j*V_(H) _(—) _(B′), where V_(H) _(—) _(B′) is selected to be less than V_(H) _(—) _(A′). This permits configurations having the same number of building blocks in the cascade to have about the same trigger voltage V_(TRIGGER). Additionally, the type of building blocks in the cascade can be selected to achieve the desired holding voltage V_(HOLDING) of the pad circuit 22.

FIGS. 9A-14B illustrate various other embodiments in a family of cascaded building blocks using Type A′ building block 201 and Type B′ building block 231. Although FIGS. 9A-14B are described in the context of Type A′ and Type B′ building blocks 201, 231 of FIGS. 7A and 8A, skilled artisans will appreciate that similar configurations can be created using the Type A and Type B building blocks 91, 92 of FIGS. 5A and 5B.

As was described earlier with reference to Table 1 and FIGS. 3A and 3B, there is a need for pad circuits which can be configured to meet the performance and design parameters required for a particular application. For example, various pads of the power management IC 20 can have different reliability and performance parameters, as shown in Table 1. FIGS. 9A-14B illustrate various cascade configurations of Type A′ and Type B′ building blocks 201, 231, which can be employed to meet different reliability and performance parameters, as will be described below. In one embodiment, the type and number of building blocks are selected during design for a particular application. In another embodiment, a multitude of building blocks are placed in the vicinity of the pad during front end fabrication, and the desired configuration is selected by changing metal layers and via connections during back end processing. In yet another embodiment, a multitude of building blocks are placed in the vicinity of the bonding pad, and the type and number of the building blocks are selected using the pad controller 23 after fabrication, as was described earlier.

FIG. 9A is a schematic block diagram of a pad circuit according to a first embodiment. The illustrated pad circuit 281 includes two Type A′ building blocks 201 connected in a cascade between the pad 42 and the node 82. The Type A′ building block 201 can be configured to have a trigger voltage V_(T) _(—) _(A′) equal to about the trigger voltage V_(T) _(—) _(B′) of the Type B′ building block 231 of FIG. 8A. However, the holding voltage V_(H) _(—) _(A′) of the Type A′ building block 201 can be configured to be greater than the holding voltage V_(H) _(—) _(B′) of the Type B′ building block 231. Thus, the pad circuit 281 can be employed, for example, in an input pad having a moderate operating voltage and requiring a relatively high holding voltage. For example, if V_(T) _(—) _(A′) is equal to about 9 V and V_(H) _(—) _(A′) is equal to about 5 V, the pad circuit 281 can have a trigger voltage of about 18 V and a holding voltage of about 10 V. Thus, the pad circuit 281 can have a holding voltage and trigger voltage appropriate for the pad VH1 in Table 1.

FIG. 9B is a circuit diagram of the pad circuit of FIG. 9A. The illustrated pad circuit 281 includes two Type A′ building blocks connected in a cascade configuration between the pad 42 and the node 82. Each Type A′ building block 201 includes a first resistor 203, a second resistor 205, a diode 204, and a NPN bipolar transistor 202 having an emitter, a base, a collector, and a plate. Additional details of the Type A′ building block 201 can be as described earlier with reference to FIG. 7A.

FIG. 10A is a schematic block diagram of a pad circuit according to a second embodiment. The illustrated pad circuit 282 includes a Type A′ building block 201 connected in a cascade with a Type B′ building block 231 between the pad 42 and the node 82. As described above, the Type A′ building block 201 can be configured to have a trigger voltage V_(T) _(—) _(A′) equal to about the trigger voltage V_(T) _(—) _(B′) of the Type B′ building block 231. However, the holding voltage V_(H) _(—) _(A′) of the Type A′ building block 201 can be configured to be greater than the holding voltage V_(H) _(—) _(B′) of the Type B′ building block 231. Thus, the pad circuit 282 can be employed, for example, in an input pad having a relatively moderate operating voltage and requiring a relatively moderate holding voltage. For example, if V_(T) _(—) _(A′) and V_(T) _(—) _(B′) are equal to about 9 V, V_(H) _(—) _(A′) is equal to about 5 V, and V_(H) _(—) _(B′) is equal to about 2.5 V, the pad circuit 282 can have a trigger voltage of about 18 V and a holding voltage of about 7.5 V. Thus, the pad circuit 282 can have a holding voltage and trigger voltage appropriate for the pad VH2 in Table 1.

FIG. 10B is a circuit diagram of the pad circuit of FIG. 10A. The illustrated pad circuit 282 includes a Type A′ building block 201 and a Type B′ building block 231 connected in a cascade configuration between the pad 42 and the node 82. The Type A′ building block 201 includes a first resistor 203, a second resistor 205, a diode 204, and a NPN bipolar transistor 202 having an emitter, a base, a collector, and a plate. Additional details of the Type A′ building block 201 can be as described earlier with reference to FIG. 7A. The Type B′ building block 231 includes a PNP transistor 232, a NPN bipolar transistor 233, a first resistor 234, a second resistor 235, a third resistor 236, and a diode 237. The PNP transistor 232 includes an emitter, a base, and a collector, and the NPN bipolar transistor 233 includes an emitter, a base, a collector and a plate. Additional details of the Type B′ building block 231 can be as described earlier with reference to FIG. 8A.

FIG. 11A is a schematic block diagram of a pad circuit according to a third embodiment. The illustrated pad circuit 283 includes two Type B′ building block 231 connected in a cascade between the pad 42 and the node 82. As described above, the Type B′ building block 231 can be configured to have a trigger voltage V_(T) _(—) _(B′) equal to about the trigger voltage V_(T) _(—) _(A′) of the Type A′ building block 201 of FIG. 7A. However, the holding voltage V_(H) _(—) _(B′) of the Type B′ building block 231 can be configured to be greater than the holding voltage V_(H) _(—) _(A′) of the Type A′ building block 201. Thus, the pad circuit 283 can be employed, for example, in an input pad having a relatively moderate operating voltage and requiring a relatively low holding voltage. For example, if V_(T) _(—) _(B′) is equal to about 9 V and V_(H) _(—) _(B′) is equal to about 2.5 V, the pad circuit 283 can have a trigger voltage of about 18 V and a holding voltage of about 5 V. Thus, the pad circuit 283 can have a holding voltage and trigger voltage appropriate for the pad VH3 in Table 1.

FIG. 11B is a circuit diagram of the pad circuit of FIG. 11A. The illustrated pad circuit 283 includes two Type B′ building blocks 231 connected in a cascade configuration between the pad 42 and the node 82. Each Type B′ building block 231 includes a PNP transistor 232, a NPN bipolar transistor 233, a first resistor 234, a second resistor 235, a third resistor 236, and a diode 237. The PNP transistor 232 includes an emitter, a base, and a collector, and the NPN bipolar transistor 233 includes an emitter, a base, a collector and a plate. Additional details of the Type B′ building block 231 can be as described earlier with reference to FIG. 8A.

FIG. 12A is a schematic block diagram of a pad circuit according to a fourth embodiment. The illustrated pad circuit 284 includes three Type A′ building blocks 201 connected in a cascade between the pad 42 and the node 82. The Type A′ building block 201 can be configured to have a trigger voltage V_(T) _(—) _(A′) equal to about the trigger voltage V_(T) _(—) _(B′) of the Type B′ building block 231 of FIG. 8A. However, the holding voltage V_(H) _(—) _(A′) of the Type A′ building block 201 can be configured to be greater than the holding voltage V_(H) _(—) _(B′) of the Type B′ building block 231. Thus, the pad circuit 284 can be employed, for example, in an output pad having a relatively high operating voltage and requiring a relatively high holding voltage. For example, if V_(T) _(—) _(A′) is equal to about 9 V and V_(H) _(—) _(A′) is equal to about 5 V, the pad circuit 284 can have a trigger voltage of about 27 V and a holding voltage of about 15 V. Thus, the pad circuit 284 can have a holding voltage and trigger voltage appropriate for the pad OVERVOLTAGE in Table 1.

FIG. 12B is a circuit diagram of the pad circuit of FIG. 12A. The illustrated pad circuit 284 includes three Type A′ building blocks connected in a cascade configuration between the pad 42 and the node 82. Each Type A′ building block 201 includes a first resistor 203, a second resistor 205, a diode 204, and a NPN bipolar transistor 202 having an emitter, a base, a collector, and a plate. Additional details of the Type A′ building block 201 can be as described earlier with reference to FIG. 7A.

FIG. 13A is a schematic block diagram of a pad circuit according to a fifth embodiment. The illustrated pad circuit 285 includes two Type B′ building blocks 231 connected in a cascade with a Type A′ building block 201 between the pad 42 and the node 82. As described above, the Type A′ building block 201 can be configured to have a trigger voltage V_(T) _(—) _(A′) equal to about the trigger voltage V_(T) _(—) _(B′) of the Type B′ building block 231. However, the holding voltage V_(H) _(—) _(A′) of the Type A′ building block 201 can be configured to be greater than the holding voltage V_(H) _(—) _(B′) of the Type B′ building block 231. Thus, the pad circuit 285 can be employed, for example, in an output pad having a relatively high operating voltage and requiring a relatively moderate holding voltage. For example, if V_(T) _(—) _(A′) and V_(T) _(—) _(B′) are equal to about 9 V, V_(H) _(—) _(A′) is equal to about 5 V, and V_(H) _(—) _(B′) is equal to about 2.5 V, the pad circuit 285 can have a trigger voltage of about 27 V and a holding voltage of about 10 V. Thus, the pad circuit 285 can have a holding voltage and trigger voltage appropriate for the pad UNDERVOLTAGE in Table 1.

FIG. 13B is a circuit diagram of the pad circuit of FIG. 13A. The illustrated pad circuit 285 includes two Type B′ building blocks 231 connected in a cascade with a Type A′ building block 201 between the pad 42 and the node 82. The Type A′ building block 201 includes a first resistor 203, a second resistor 205, a diode 204, and a NPN bipolar transistor 202 having an emitter, a base, a collector, and a plate. Additional details of the Type A′ building block 201 can be as described earlier with reference to FIG. 7A. Each Type B′ building block 231 includes a PNP transistor 232, a NPN bipolar transistor 233, a first resistor 234, a second resistor 235, a third resistor 236, and a diode 237. The PNP transistor 232 includes an emitter, a base, and a collector, and the NPN bipolar transistor 233 includes an emitter, a base, a collector and a plate. Additional details of the Type B′ building block 231 can be as described earlier with reference to FIG. 8A.

FIG. 14A is a schematic block diagram of a pad circuit according to a sixth embodiment. The illustrated pad circuit 286 includes three Type B′ building block 231 connected in a cascade between the pad 42 and the node 82. As described above, the Type B′building block 231 can be configured to have a trigger voltage V_(T) _(—) _(B′) equal to about the trigger voltage V_(T) _(—) _(A′) of the Type A′ building block 201 of FIG. 7A. However, the holding voltage V_(H) _(—) _(B′) of the Type B′ building block 231 can be configured to be greater than the holding voltage V_(H) _(—) _(A′) of the Type A′ building block 201. Thus, the pad circuit 286 can be employed, for example, in an input pad having a relatively high operating voltage and requiring a relatively low holding voltage. For example, if V_(T) _(—) _(B′) is equal to about 9 V and V_(H) _(—) _(B′) is equal to about 2.5 V, the pad circuit 286 can have a trigger voltage of about 27 V and a holding voltage of about 7.5 V. Thus, the pad circuit 286 can have a holding voltage and trigger voltage appropriate for the pad VH4 in Table 1.

FIG. 14B is a circuit diagram of the pad circuit of FIG. 14B. The illustrated pad circuit 286 includes three Type B′ building block 231 connected in a cascade between the pad 42 and the node 82. Each Type B′ building block 231 includes a PNP transistor 232, a NPN bipolar transistor 233, a first resistor 234, a second resistor 235, a third resistor 236, and a diode 237. The PNP transistor 232 includes an emitter, a base, and a collector, and the NPN bipolar transistor 233 includes an emitter, a base, a collector and a plate. Additional details of the Type B′ building block 231 can be as described earlier with reference to FIG. 8A.

In the embodiments shown in FIGS. 9A-14B, cascaded building block configurations employ Type A′ and Type B′ building blocks 201, 231. However, one or more additional building block types can be included. For example, a Type C′ building block having a holding voltage V_(H) _(—) _(C′) and a trigger voltage V_(T) _(—) _(C′) can be utilized. The pad circuit 22 can combine i number of Type A′ building blocks, j number of Type B′ building blocks, and k number of Type C′ building blocks such that the pad circuit 22 has a trigger voltage V_(TRIGGER) roughly equal to about i*V_(T) _(—) _(A′)+j*V_(T) _(—) _(B′)+k*V_(T) _(—) _(C′), and a holding voltage V_(HOLDING) roughly equal to about i*V_(H) _(—) _(A′)+j*V_(H) _(—) _(B′)+k*V_(H) _(—) _(C′). Providing additional types of building block can increase the multitude of configurations of the cascade at the expense of an increase in design complexity.

FIG. 15 is a circuit diagram illustrating a pad circuit building block in accordance with yet another embodiment. The Type C′ building block 291 can be connected in a cascade with other building blocks between the pad 42 and the node 82. The illustrated Type C′ building block 291 includes a first resistor 293, a second resistor 295, a diode 294, and a PNP bipolar transistor 292 having an emitter, a base, a collector, and a plate. The PNP bipolar transistor 292 can have a structure similar to that of the PNP bipolar transistor 160 of FIG. 6C.

The diode 294 includes an anode electrically connected to the node 82, and a cathode electrically connected to the emitter of the PNP bipolar transistor 292 and to a first end of the first resistor 293 at a node N₅. The node N₅ can be electrically connected to another building block in a cascade, such as the cascaded building blocks of FIGS. 4A and 4B, or to the pad 42. The first resistor 293 includes a second end electrically connected to the base of the PNP bipolar transistor 292. The first resistor 293 can have, for example, a resistance between about 11Ω and about 85Ω. In one embodiment, the first resistor 293 is implemented using a multi-finger array to achieve the target resistance, such as an array of six fingers each having a resistance selected from the range of about 66Ω and about 510Ω. The second resistor 295 includes a first end electrically connected to the plate of the PNP bipolar transistor 292, and a second end electrically connected to the collector of the NPN bipolar transistor 292 at a node N₆. The second resistor 295 can have, for example, a resistance between about 200Ω and about 50 kΩ. The node N₆ can be electrically connected to another building block in a cascade or to the node 82.

The pad circuit 22 can be, for example, any of the pad circuits 22 a-22 p shown in FIG. 2, and the pad 42 can be any of the pads 42 a-42 p, including, for example, low-impedance output pads, high-impedance input pads, and low-impedance power pads. The node 82 can be, for example, a low impedance node or pad of the power management IC 20 configured to handle a relatively large shunted current. A transient signal event can be received at the pad 42. If the transient signal event has a voltage that is negative with respect to the node 82, the diode 294 can provide current which can aid in protecting the power management IC 20.

If the transient signal event has a voltage which is positive with respect to the node 82, the PNP bipolar transistor 292 can aid in providing transient signal protection. The trigger voltage of the Type C′ building block V_(T) _(—) _(C′) can be based on the collector-emitter breakdown voltage of the PNP bipolar transistor 292. The Type C′ building block can have a holding voltage V_(H) _(—) _(C′) greater than either the holding voltage V_(H) _(—) _(A′) or V_(H) _(—) _(B′). During normal operation, the absence of the LDD can make the leakage of the PNP bipolar transistor 292 low, even at relatively high temperatures. The PNP bipolar transistor 292 can have a lower leakage current as compared to a similarly sized PMOS transistor.

FIG. 16A is a schematic block diagram of a pad circuit according to a seventh embodiment. The illustrated pad circuit 297 includes a Type C′ building block 291, a Type B′ building block 231, and a Type C′ building block 291 connected in a cascade between the pad 42 and the node 82. As described above, the holding voltage V_(H) _(—) _(C′) of the Type C′ building block 291 can be configured to be greater than the holding voltage V_(H) _(—) _(B′) of the Type B′ building block 231 or the holding voltage V_(H) _(—) _(A′) of the Type A′ building block 201. Furthermore, in certain processes, the leakage of the Type C′ building block 291 can be less than that of the Type A′ and Type B′ building blocks 201, 231. Thus, the pad circuit 297 can be used, for example, in a very low leakage power pad having a relatively high operating voltage and requiring a relatively high holding voltage. For example, if V_(T) _(—) _(A′) and V_(T) _(—) _(B′) are equal to about 9 V, V_(T) _(—) _(C′) is equal to about 10 V, V_(H) _(—) _(B′) is equal to about 2.5 V, and V_(H) _(—) _(C′) is equal to about 10V, the pad circuit 285 can have a trigger voltage of about 29 V and a holding voltage of about 22.5 V. Thus, the pad circuit 297 can have a holding voltage and trigger voltage appropriate for the pad Vcc in Table 1. Additionally, in certain processes, the leakage current of the pad circuit 297 can be less than certain pad circuit configurations using only Type A′ and Type B′ building blocks, and thus pad circuit configurations with Type C′ building blocks can be employed for very low leakage pads.

FIG. 16B is a circuit diagram of the pad circuit of FIG. 16A. The illustrated pad circuit 297 includes a Type C′ building block 291, a Type B′ building block 231, and a Type C′ building block 291 connected in a cascade between the pad 42 and the node 82. Each Type C′ building block 291 includes a first resistor 293, a second resistor 295, a diode 294, and a PNP bipolar transistor 292 having an emitter, a base, a collector, and a plate. Additional details of the Type C′ building block 291 can be as described earlier with reference to FIG. 15. The Type B′ building block 231 includes a PNP transistor 232, a NPN bipolar transistor 233, a first resistor 234, a second resistor 235, a third resistor 236, and a diode 237. The PNP transistor 232 includes an emitter, a base, and a collector, and the NPN bipolar transistor 233 includes an emitter, a base, a collector and a plate. Additional details of the Type B′ building block 231 can be as described earlier with reference to FIG. 8A.

FIG. 17A is a perspective view of one implementation of the pad circuit of FIG. 12B. The illustrated pad circuit 300 includes a bonding pad 305, a first Type A′ building block 301, a second Type A′ building block 302, and a third Type A′ building block 303 connected in a cascade. The layout of the first Type A′ building block 301 is configured such that the first Type A′ building block 301 can fit below the bonding pad 305. The second and Type A′ building blocks 302, 303 have layouts extending outside the bonding pad area.

During back-end fabrication (for example, fabrication of metal layers), building blocks can be included in a cascade configuration with the first Type A′ building block. Thus, for example, the pad circuit 300 can be configured to have the configuration shown in FIG. 9B by changing the metal layers. Furthermore, additional building blocks, such as a Type B′ building block can be placed adjacent to the pad 305, and can be included in the cascade by changing metal layers. Thus, an IC using the pad circuit 300, such as the power management IC 20, can be configured for a particular electronic system or application.

As will be described in further detail below with reference to FIGS. 17B-17I, the pad circuit 300 can advantageously be constructed with three metal layers, thereby permitting fabrication in processes with limited numbers of metal layers. Moreover, the pad circuit 300 can be implemented in a small circuit area, and a large portion of the pad circuit 300 can be positioned directly under the bonding pad 305.

FIG. 17B is a cross section of the pad circuit 300 of FIG. 17A taken along the line 17B-17B. The first Type A′ building block 301 includes a substrate 307, plates 309, a deep n-well 310, n-wells 311, contacts 312, a first metal layer 313, first vias 314, a second metal layer 315, second vias 316, a third metal layer 317, and passivation layer 318. In contrast to the Type A′ building block 201 shown in FIG. 7B, the first Type A′building block 301 is illustrated with back end processing. The deep n-well 310 and n-wells 311 can electrically isolate the first Type A′ building block 301 from other building blocks, such as the second and third Type A′ building blocks 302, 303. Additional details of the base layers of the first Type A′ building block can be similar to those described earlier with reference to FIG. 7B.

FIG. 17C is a cross section of the pad circuit of FIG. 17A taken along the line 17C-17C. The second Type A′ building block 302 can be formed in the same substrate 307 as the first Type A′ building block 301. The second Type A′ building block 302 can include plates 309, a deep n-well 310, n-wells 311, contacts 312, a first metal layer 313, first vias 314, a second metal layer 315, second vias 316, and a third metal layer 317. Additional details of the base layers of the second Type A′ building block 302 can be similar to those described earlier with reference to FIG. 7B. Skilled artisans will appreciate that the geometries of first Type A′ building block 301 and the second Type B′ building block 302 can be different. For example, the plates 309 of the first Type A′ building block 301 can have different plate widths than the plates 309 of the second Type A′ 302, as can been seen in FIG. 17E.

FIG. 17D is a cross section of the pad circuit of FIG. 17A taken along the line 17D-17D. The third Type A′ building block 303 can be formed in the same substrate 307 as the first and second Type A′ building blocks 301, 302. The third Type A′ building block 303 can include plates 309, a deep n-well 310, n-wells 311, contacts 312, a first metal layer 313, first vias 314, a second metal layer 315, second vias 316, and a third metal layer 317. Additional details of the third Type A′ building block 303 can be as described earlier in connection with FIG. 7B.

FIG. 17E is a top plan view of the active and polysilicon layers of the pad circuit of FIG. 17A. FIG. 17F is a top plan view of the contact and first metal layers of the pad circuit of FIG. 17A. As shown in FIG. 17E, each of the building blocks 301-303 includes a plurality of rows of emitters 320, 322 and a plurality of rows of collectors 321, when viewed from above. The rows of emitters 320, 322 and collectors 321 extend substantially parallel to one another. As shown in FIG. 17F, the emitters 320 on both of the peripheries of the pad circuit 300 can have a single row of contacts, while emitters 322 not on the peripheries of the pad circuit 300 and collectors 321 can have a double row of contacts.

The contacts of the emitters 320, collectors 321 and emitters 322 can be spaced so as to permit first, and second vias to be stacked, as shown in FIGS. 17F-17H. The n-diffusion resistors 323 can have a resistance similar to that described above with reference to FIG. 7A. Each n-diffusion resistor 323 can have, for example, a width W_(R) of 0.7 μm and a length L_(R) of 9 μm.

As shown in FIGS. 17E-17F, a guard ring 325 can be connected through two rows of contacts. Additionally, a substrate guard ring 326 can be contacted with a double row of contacts. The plates 327 a and plates 327 b can each have ten fingers, and each plate can have a plate length of, for example, about 0.5 μm. The plates 327 a can have a width of, for example, about 615 μm, and the plates 327 b can have a width of, for example, about 300 μm. The contact to diffusion overlap can be, for example, about 2 μm.

FIG. 17G is a top plan view of the first metal layer 313 and first via layer 314 of the pad circuit of FIG. 17A. Four rows of vias 340 can be provided to contact the drains of NPN bipolar transistors. FIG. 17H is a top plan view of the first via layer 314, the second metal layer 315 and the second via layer 316 of the pad circuit of FIG. 17A. FIG. 17I is a top plan view of the third metal layer 317 and the second via layer 316 of the pad circuit of FIG. 17A.

Although FIGS. 17A-17I describe the construction and dimensions of one particular layout for a cascaded pad circuit, skilled artisans will appreciate that this example was for purposes of illustration. Pad circuit building blocks can be formed in a variety of ways, and can have different circuit layouts depending on a variety of factors, including, for example, fabrication process and application of the pad circuit.

FIG. 18A is a perspective view of one implementation of the pad circuit of FIG. 11B. The illustrated pad circuit 400 includes a first Type B′ building block 401 and a second Type B′ building block 402. The layout of the first and second Type B′ building blocks 401, 402 is configured such that the both Type B′ building blocks 401, 402 can fit below a bonding pad, which has been omitted from FIG. 18A for clarity. Additional building blocks, such as a Type A′ building block, can be placed adjacent to the bonding pad, and can be included in the cascade, for example, by a change metal layers. Thus, an IC using the pad circuit 400, such as the power management IC 20, can be configured for a particular electronic system or application.

FIG. 18B is a cross section of the pad circuit of FIG. 18A taken along the line 18B-18B. The first Type B′ building block 401 includes a substrate 407, plates 409, a deep n-wells 410, n-wells 411, contacts 412, a first metal layer 413, first vias 414, a second metal layer 415, second vias 416, a third metal layer 417, and passivation layer 418. In contrast to the Type B′ building block 231 shown in FIG. 5B, the Type B′ building blocks 401, 402 of FIG. 18B are illustrated with back end processing. The deep n-wells 410 and n-wells 411 can provide electrically isolation of building blocks, such as between first and second Type B′ building blocks 401, 402, as well as electrical isolation of each building block from the substrate 407. Additional details of the base layers of the first Type B′ building block can be similar to those described earlier in connection with FIG. 8B.

The foregoing description and claims may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the Figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

Applications

Devices employing the above described schemes can be implemented into various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, etc. Examples of the electronic devices can also include memory chips, memory modules, circuits of optical networks or other communication networks, and disk driver circuits. The consumer electronic products can include, but are not limited to, a mobile phone, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, an automobile, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi functional peripheral device, a wrist watch, a clock, etc. Further, the electronic device can include unfinished products.

Although this invention has been described in terms of certain embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Moreover, the various embodiments described above can be combined to provide further embodiments. In addition, certain features shown in the context of one embodiment can be incorporated into other embodiments as well. Accordingly, the scope of the present invention is defined only by reference to the appended claims. 

1. An apparatus for providing transient signal protection, the apparatus comprising: a substrate; a well formed on a first surface of the substrate, wherein the well has a doping of a first type, and wherein the well is configured to operate as a base for a first transistor; an emitter region formed in the well, wherein the emitter region has a doping of a second type opposite that of the first type, and wherein the emitter region is configured to operate as an emitter for the first transistor; a collector region formed at least partially in the well and spaced away from the emitter region to define a spacing, wherein the collector region has a doping of the second type, and wherein the collector region is configured to operate as a collector of the first transistor; a first spacer and a second spacer positioned adjacent the well between the emitter and the collector, wherein the first spacer and the second spacer are dielectric; and a conductive plate positioned adjacent the well and between the first spacer and the second spacer, wherein a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.
 2. The apparatus of claim 1, wherein the doping of the first type is an n-type dopant, and wherein the doping of the second type is a p-type dopant.
 3. The apparatus of claim 1, wherein the doping of the first type is a p-type dopant, and wherein the doping of the second type is an n-type dopant.
 4. The apparatus of claim 3, further comprising an isolation layer beneath the well.
 5. The apparatus of claim 4, wherein the isolation layer comprises deep-well.
 6. The apparatus of claim 3, further comprising a first n-well positioned adjacent the well on a first side, and a second n-well positioned adjacent the well on a second side.
 7. The apparatus of claim 6, wherein the first n-well comprises a first PNP emitter region formed in the first n-well, and wherein a portion of the collector region is formed in the first n-well, and wherein the first PNP emitter region is configured to operate as an emitter of a second transistor, and wherein the first n-well is configured to operate as a base of the second transistor and the collector of the first transistor, and wherein the well having a doping of the first type is configured to operate as a collector of the second transistor.
 8. The apparatus of claim 7, wherein the second n-well comprises a first guard ring.
 9. The apparatus of claim 8, wherein the first guard ring and the first PNP emitter region are electrically connected.
 10. The apparatus of claim 9, wherein the first guard ring, the first PNP emitter region, and the first n-well are electrically connected.
 11. The apparatus of claim 8, further comprising: a p-well formed on the first surface of the substrate, wherein the p-well is configured to operate as a base for a third transistor, an NPN emitter region formed in the p-well, wherein the NPN emitter region has a n-type doping, and wherein the NPN emitter region is configured to operate as an emitter for the third transistor, an NPN collector region formed at least partially in the p-well and spaced away from the NPN emitter region to define a spacing of the third transistor, wherein the NPN collector region has a n-type doping, and wherein the NPN collector region is configured to operate as a collector of the third transistor, a first spacer and a second spacer of the third transistor positioned adjacent the p-well between the NPN emitter and the NPN collector, wherein the first spacer and the second spacer of the third transistor are dielectric, and a conductive plate of the third transistor positioned adjacent the p-well and between the first spacer and the second spacer of the third transistor, wherein a doping adjacent the first spacer, the second spacer, and the plate of the third transistor consists essentially of the first type.
 12. The apparatus of claim 11, further comprising a third n-well positioned adjacent the p-well on a first side, wherein the third n-well includes a second PNP emitter region formed in the third n-well, and wherein a portion of the NPN collector region is formed in the third n-well, and wherein the second PNP emitter region is configured to operate as an emitter of a fourth transistor, and wherein the third n-well is configured to operate as a base of the fourth transistor and the collector of the third transistor, and wherein the p-well is configured to operate as a collector of the fourth transistor.
 13. The apparatus of claim 12, further comprising a fourth n-well positioned adjacent the p-well on a second side, wherein the fourth n-well comprises a second guard ring, and wherein the second guard ring, the second PNP emitter region, and the emitter region of the first transistor are electrically connected.
 14. The apparatus of claim 13, further comprising a bonding pad positioned adjacent the first surface of the substrate, wherein the first and second transistors form a first subcircuit and the third and fourth transistors form a second subcircuit, and wherein the first and second subcircuits are disposed so as to fit under the bonding pad.
 15. The apparatus of claim 1, wherein the distance between the emitter and the plate below the first spacer is selected to be in the range of about 0.1 μm to about 1.0 μm, and wherein the distance between the collector and the plate below the second spacer is selected to be in the range of about 0.1 μm to about 1.0 μm.
 16. The apparatus of claim 1, wherein the plate comprises polysilicon.
 17. The apparatus of claim 1, wherein the plate length is selected from the range of about 0.25 μm to about 0.6 μm and the plate width is selected from the range of about 30 μm to about 50 μm.
 18. The apparatus of claim 1, further comprising a resistor having a first end electrically connected to the plate and a second end electrically connected to the emitter region formed in the well.
 19. The apparatus of claim 18, wherein the resistor comprises n-diffusion.
 20. The apparatus of claim 18, wherein the resistor comprises polysilicon.
 21. The apparatus of claim 18, wherein the resistor has a resistance selected from the range of about 200Ω to about 50 kΩ.
 22. The apparatus of claim 1, further comprising an oxide layer disposed between the conductive plate and the well.
 23. The apparatus of claim 1, wherein the doping adjacent the first spacer, the second spacer, and the plate does not include a lightly doped drain (LDD) region.
 24. The apparatus of claim 1, wherein the collector region is formed completely in the well region.
 25. An apparatus for providing transient signal protection, the apparatus comprising: a substrate means; a well means formed on a first surface of the substrate means, wherein the well means has a doping of a first type, and wherein the well means is configured to operate as a base for a first transistor; an emitter means formed in the well means, wherein the emitter means has a doping of a second type opposite that of the first type, and wherein the emitter means is configured to operate as an emitter for the first transistor; a collector means formed at least partially in the well means and spaced away from the emitter means to define a spacing, wherein the collector means has a doping of the second type, and wherein the collector means is configured to operate as a collector of the first transistor; a first spacing means and a second spacing means positioned adjacent the well means between the emitter means and the collector means; and a plate means positioned adjacent the well means and between the first spacing means and the second spacing means, wherein a doping adjacent the first spacing means, the second spacing means, and the plate means consists essentially of the first type.
 26. The apparatus of claim 25, further comprising an isolating means beneath the well means.
 27. The apparatus of claim 25, wherein the doping of the first type is an n-type dopant, and wherein the doping of the second type is a p-type dopant.
 28. The apparatus of claim 25, wherein the doping of the first type is a p-type dopant, and wherein the doping of the second type is an n-type dopant.
 29. The apparatus of claim 28, further comprising an n-well means positioned adjacent the well means.
 30. The apparatus of claim 29, wherein the n-well means comprises a PNP emitter means formed in the n-well means, and wherein the PNP emitter means is configured to operate as an emitter of a second transistor, and wherein the n-well means is configured to operate as a base of the second transistor, and wherein the well means is configured to operate as a collector of the second transistor.
 31. The apparatus of claim 25, further comprising a resistor means having a first end electrically connected to the plate means and a second end electrically connected to the emitter means formed in the well means.
 32. The apparatus of claim 25, further comprising a dielectric means disposed between the plate means and the well means.
 33. A method for providing protection from transient electrical events comprising: providing a substrate; forming a well having a doping of a first type on a first surface of the substrate; forming a plate adjacent the well; forming first and second spacers adjacent the well, wherein the plate is positioned between the first and second spacers, and wherein a length of the plate and a length of the first and second spacers define a first distance; forming an emitter and a collector at least partially in the well, wherein the emitter and the collector have a doping of a second type opposite that of the first type, and wherein the emitter and collector are spaced apart by the first distance; and configuring the well, the emitter and the collector, respectively, to operate as the base, emitter, and collector of a bipolar transistor for providing protection from transient electrical events, wherein the method does not include forming a lightly doped drain (LDD) region in the well.
 34. The method of claim 33, wherein the doping of the first type is an n-type dopant, and wherein the doping of the second type is a p-type dopant.
 35. The method of claim 33, wherein the doping of the first type is a p-type dopant, and wherein the doping of the second type is an n-type dopant.
 36. The method of claim 33, further comprising masking an area of the first and second spacers of the well such that formation of the LDD region in the well is prevented when LDD regions are being formed for field effect transistors of the same substrate. 